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42 Cards in this Set
- Front
- Back
On a D-Latch, what does the data input control?
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Controls what the next state should be.
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On a D-Latch, what does the clock input control?
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Controls when the state should change.
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A D-latch is transparent when
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CLK=1
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A D flip flip copies D to Q when?
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On the rising edge of the clock, and remembers its state at all other times.
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What kind of flip-flops reset themselves as soon as RESET becomes true, independent of CLK?
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Asynchronously resettable.
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What kind of flip-flops reset themselves only on the rising edge of CLK?
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Synchronously resettable.
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What is a glitch?
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When the clock switches at an incorrect time.
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What is a race condition?
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When a circuit has certain gates that are slower than others.
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What do the outputs of Moore machines depend on?
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The current state only.
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What do the outputs of Mealy machines depend on?
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Inputs as well as the current state.
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What is clock skew?
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The variation in time of the clock reaching all flip-flops; the variation in clock edges.
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What are the two most commonly-used hardware description languages?
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Verilog and VHDL.
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The outputs of sequential logic depend on what?
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Both current and prior input values.
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What is a register?
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A bank of N flip-flops that share a common CLK input, so that all bits of the register are updated at the same time.
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What is setup time?
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Time for inputs to stabilize before the rising edge of the clock.
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What is hold time?
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Time the inputs must remain stable after the rising edge of the clock.
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What is the aperture time?
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The sum of the setup and hold times.
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What is the critical path?
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The slowest path from the inputs to the outputs. The sum of the propagation delays over that path.
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What is the clock-to-Q delay?
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The time required for the clock to propagate to the outputs.
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What is a hold time constraint?
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The input must not change until some hold time after the rising edge of the clock.
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What is a hold time violation?
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A violation of a hold time constraint.
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True or false: a reliable flip-flop must have a hold time shorter than its contamination delay?
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True!
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The contamination delay of a circuit must be greater than
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The hold time + clock skew - clock-to-q.
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What is the clock period?
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The time between rising edges of a repetitive clock signal.
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To avoid hold time violations, what must be true about the contamination delay?
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It must be >= hold time + clock skew - clock-to-q contamination delay.
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What is metastability?
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When the output takes on a voltage in the forbidden zone. Eventually it will resolve the output to a stable state.
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What is the minimum clock period?
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Min clock period is greater than or equal to c-to-q propagation delay + propagation delay + setup time.
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What is the minimum contamination delay through the logic?
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Is >= hold time - contamination from c-to-q,
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What is the minimum clock cycle time?
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>= t_pcq + t_pd + t_setup
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What does a flip-flop do on the rising edge of the clock?
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Copies D to Q.
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What is the aperture time of a circuit?
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The sum of the setup and hold times.
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The total time for which the inputs must remain stable is called the
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aperture time
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What is a setup time constraint?
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The input must settle no later than the setup time before the next clock edge.
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What is a hold time constraint?
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The input must not change until some hold time after the rising edge of the clock.
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In a D latch, which is inverted--the clock or D?
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D
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In a D flip-flop, is the clock inverted on the master or slave D-latch?
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On the master.
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On an SR latch, does R connect directly to Q or Q-not?
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Q
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Contamination delay
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The minimum time from when an input changes until any output starts to change its value.
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Propagation delay
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The maximum time from when an input changes until the output reaches its final value.
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What does ^ mean in Verilog?
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XOR
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How do you make an XOR in Verilog?
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^
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True or false: In a Verilog always statement, <= indicates a blocking assignment and = indicates a nonblocking assignment.
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False. In a Verilog always statement, = indicates a blocking assignment and <= indicates a nonblocking assignment.
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